Digital logic is extensively used in data and signal processing systems. Typically, the timing of these systems is controlled by a master clock. Specifically, one master clock provides a timing signal having a master frequency to each of the system's elements. Clock dividers are often used to divide the master frequency resulting in clock signals having lower frequencies than the master frequency. Thus the master frequency is generally selected to be the highest frequency required by any of the elements of the system.
However, the master frequency also limits the speed at which the system can operate. For instance, in many applications such as running iterative loops, the master frequency unnecessarily limits the speed at which the loop operates. For example, refer to the iterative loop shown in FIG. 1. Two data paths are provided as inputs to the loop and are designated DATAIN1 and DATAIN2. Specifically, DATAIN1 and DATAIN2 are inputs to data operation blocks 5 and 6 respectively. A data operation block may be, for instance, an incrementor, adder, subtractor, multiplier, etc., which are well known in the art. These data operations are typically performed by combinational circuits of logic gates. Therefore, they respond almost immediately to any changes in the contents of their respective inputs, DATAIN1 and DATAIN2. However, register 4 which completes the iterative loop and has an input coupled to the output of data operation block 6, ignores any change at its input until it receives a clock pulse from the master clock 3. Register 4 inputs new data from data operation block 6 and outputs any data stored therein upon either the leading edge or the trailing edge of each clock pulse. Thus, the data operation block 5 which has an input coupled to the output of register 4 does not receive a new input until a clock pulse is received by register 4. Therefore, the master clock frequency limits the rate at which data can be output from the loop as well.
To solve this problem, a higher frequency waveform must be provided to register 4 to speed up the operation. For example, a second master clock can be provided to generate an additional timing signal with the same master frequency. If the second clock operates at 90.degree. out-of-phase with the master clock, then the frequency of the combined clock pulses received by register 4 is doubled. The iterative loop circuit can, therefore, run at twice the speed using timing signals from both clocks rather than using only the one master clock. However adding an additional clock is costly and complicated to integrate the additional timing signal into the existing circuit.
Alternatively, a higher frequency master clock could be used so that iterative loops and similar applications would not be limited by a slower clock. However, a higher frequency master clock is often more expensive than a lower frequency clock. Furthermore, it will become necessary to provide clock divide circuits to generate lower frequencies required by other system applications that would not otherwise have been necessary if the master clock with a lower master frequency was selected.
Since the addition of duplicate or substitute hardware is costly and complex to integrate into the system, there is a need to provide a simple clocking scheme which does not require a higher frequency waveform than the master clock frequency. The present invention fulfills this need.